1. Field of the Invention
The present invention relates to a data processing method that binarizes a data signal output from a delay circuit and a solid-state image pickup device using the method.
Priority is claimed on Japanese Patent Application No. 2010-023487, filed Feb. 4, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
FIG. 14 is a view illustrating a portion of an analogue-digital (A/D) converter circuit for counting of a time, i.e., a so-called Time to Digital Converter (TDC) type A/D converter circuit in accordance with the related art. The circuit illustrated in FIG. 14 includes an annulus ring delay circuit 201, which includes a plurality of inverting elements (NAND0, INV1 through INV8) which are connected to each other so as to be formed into a ring shape, a latch circuit 202, which holds outputs from the annulus ring delay circuit 201, a binarizing circuit (i.e., a full-encoder circuit) 203, which binarizes values held by the latch circuit 202, a counter circuit 204, which counts with respect to one of the outputs from the annulus ring delay circuit 201 as a count clock, and a memory circuit 205, which holds an output from the binarizing circuit 203 and an output from the counter circuit 204.
The A/D conversion operation in accordance with the related art will be described below. FIG. 15 is a view illustrating an operation timing of the circuit illustrated in FIG. 14. A logic state of a start pulse StartP changes from an L-state to an H-state, thereby logic states of the inverting elements included in the annulus ring delay circuit 201 sequentially change. Accordingly, pulses surround around the annulus ring delay circuit 201. After a predetermined time period, the latch circuit 202 holds (latches) the outputs from the annulus ring delay circuit 201. As illustrated in FIG. 15, the outputs from the annulus ring delay circuit 201, respectively, correspond to any one of 18 states (i.e., a state 0 through a state 17). The outputs from the annulus ring delay circuit 201 held (i.e., latched) by the latch circuit 202 are fully encoded (i.e., parallelly encoded) by a binarizing circuit 203 to generate binary encoded data (i.e., a lower counter value). The counter circuit 204 performs counting of the output of an inverting element INV8 as a count clock, thereby generating a count value (i.e., an upper counter value). The lower counter value and the upper counter value are stored in a memory circuit 205 to be output to the subsequent circuit in the form of digital data.
A typical data processing method in accordance with the related art includes a method that a data signal is fully encoded (i.e., parallelly encoded) by using a full-encoder circuit (hereinafter referred to as the “encoder circuit”). In this method, an output of each of the inverting elements included in the delay circuit is parallelly input into the encoder circuit and, based on a logic state thereof, binary encoded data is generated.
The above-described A/D converter circuit is applied to, for example, a solid-state image pickup device. Japanese Unexamined Patent Application, First Publication No. 2005-347931 discloses an A/D converter circuit that is arranged for each of rows of pixels in order to perform an A/D conversion outputs from the pixels.
In the above-described fully-encoding type data processing method, the necessary number of input terminals in the encoder circuit corresponds to the number of data signals. More specifically, in a case of obtaining 2-bit binary encoded data, 4 input terminals are required. In a case of obtaining 4-bit binary encoded data, 16 input terminals are required. Consequently, it is required to prepare the number of signal lines corresponding to the number of input terminals in order to connect the latch circuit with the encoder circuit. In a case where the encoder circuit for outputting the 4-bit binary encoded data is installed in, for example, a so-called column unit, having an area including narrow pitches, of the solid-state image pickup device, the encoder circuit is required to be built-in with pitches approximately equal to pixel pitches (i.e., equal to or less than a several um).